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| author | William D. Jones <thor0505@comcast.net> | 2020-11-17 13:01:57 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | 9cb0bae1b27928202fa9ce6d494f7f6aaa36563a (patch) | |
| tree | 7f03bdd48acdaa972827bcc7fe69ab047e91cb84 /tests/arch/machxo2/logic.ys | |
| parent | b87f6a09069eb2b1dce3ff197691e5f2e76dff38 (diff) | |
| download | yosys-9cb0bae1b27928202fa9ce6d494f7f6aaa36563a.tar.gz yosys-9cb0bae1b27928202fa9ce6d494f7f6aaa36563a.tar.bz2 yosys-9cb0bae1b27928202fa9ce6d494f7f6aaa36563a.zip | |
machxo2: Add test/arch/machxo2 directory (test does not pass).
Diffstat (limited to 'tests/arch/machxo2/logic.ys')
| -rw-r--r-- | tests/arch/machxo2/logic.ys | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/tests/arch/machxo2/logic.ys b/tests/arch/machxo2/logic.ys new file mode 100644 index 000000000..c5d2fb08e --- /dev/null +++ b/tests/arch/machxo2/logic.ys @@ -0,0 +1,8 @@ +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 9 t:LUT4 +select -assert-none t:LUT4 %% t:* %D |