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| author | David Shah <dave@ds0.me> | 2020-10-01 11:15:54 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-10-15 08:52:15 +0100 |
| commit | 4d584d9319e87023f3aee9f9bc86a036f670478c (patch) | |
| tree | 6c80347ec72c1dc36f5d77f0ce5b204a910bbfb7 /tests/arch/nexus/mul.ys | |
| parent | f9ed9786bf8743e96aafb42838cfef5e18e35f29 (diff) | |
| download | yosys-4d584d9319e87023f3aee9f9bc86a036f670478c.tar.gz yosys-4d584d9319e87023f3aee9f9bc86a036f670478c.tar.bz2 yosys-4d584d9319e87023f3aee9f9bc86a036f670478c.zip | |
synth_nexus: Initial implementation
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'tests/arch/nexus/mul.ys')
| -rw-r--r-- | tests/arch/nexus/mul.ys | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/tests/arch/nexus/mul.ys b/tests/arch/nexus/mul.ys new file mode 100644 index 000000000..27ea3e04e --- /dev/null +++ b/tests/arch/nexus/mul.ys @@ -0,0 +1,28 @@ +read_verilog ../common/mul.v +hierarchy -top top +proc + +design -save read + +equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 7 t:CCU2 +select -assert-max 5 t:WIDEFN9 +select -assert-max 62 t:LUT4 + +select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D + +design -load read + +equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +stat + +select -assert-count 7 t:CCU2 +select -assert-max 12 t:WIDEFN9 +select -assert-max 58 t:LUT4 + +select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D |