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| author | Lofty <dan.ravensloft@gmail.com> | 2021-04-12 10:33:40 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-04-17 20:54:58 +0200 |
| commit | dce037a62c5bda9a8256d271d39b06be366120e8 (patch) | |
| tree | 67d022cbceb487f5359215d7c9ca51959100f549 /tests/arch/quicklogic/mux.ys | |
| parent | a58571d0fe8971cb7d3a619a31b2c21be6d75bac (diff) | |
| download | yosys-dce037a62c5bda9a8256d271d39b06be366120e8.tar.gz yosys-dce037a62c5bda9a8256d271d39b06be366120e8.tar.bz2 yosys-dce037a62c5bda9a8256d271d39b06be366120e8.zip | |
quicklogic: ABC9 synthesis
Diffstat (limited to 'tests/arch/quicklogic/mux.ys')
| -rw-r--r-- | tests/arch/quicklogic/mux.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/mux.ys index 632d14687..ea17fa99b 100644 --- a/tests/arch/quicklogic/mux.ys +++ b/tests/arch/quicklogic/mux.ys @@ -30,13 +30,13 @@ proc equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 4 t:LUT2 +select -assert-count 1 t:LUT1 select -assert-count 1 t:LUT3 select -assert-count 2 t:mux4x0 select -assert-count 11 t:inpad select -assert-count 1 t:outpad -select -assert-none t:LUT2 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D +select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D design -load read hierarchy -top mux16 |