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author | N. Engelhardt <nak@yosyshq.com> | 2023-02-20 18:27:24 +0100 |
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committer | GitHub <noreply@github.com> | 2023-02-20 18:27:24 +0100 |
commit | c8966722d2fcbff67a2724f921a3692ab63d83ec (patch) | |
tree | 28ebdac931b3e2614d8d82c9c3ec623b9e553dd5 /tests/arch/xilinx/asym_ram_sdp_read_wider.v | |
parent | f0116330bce4e787dcbbf81c6e901a44715589a8 (diff) | |
parent | f80920bd9f1b235693d61427d1532b8465fce12c (diff) | |
download | yosys-c8966722d2fcbff67a2724f921a3692ab63d83ec.tar.gz yosys-c8966722d2fcbff67a2724f921a3692ab63d83ec.tar.bz2 yosys-c8966722d2fcbff67a2724f921a3692ab63d83ec.zip |
Merge pull request #3403 from KrystalDelusion/mem-tests
Diffstat (limited to 'tests/arch/xilinx/asym_ram_sdp_read_wider.v')
-rw-r--r-- | tests/arch/xilinx/asym_ram_sdp_read_wider.v | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/tests/arch/xilinx/asym_ram_sdp_read_wider.v b/tests/arch/xilinx/asym_ram_sdp_read_wider.v new file mode 100644 index 000000000..8743209e3 --- /dev/null +++ b/tests/arch/xilinx/asym_ram_sdp_read_wider.v @@ -0,0 +1,72 @@ +// Asymmetric port RAM +// Read Wider than Write. Read Statement in loop +//asym_ram_sdp_read_wider.v +module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB); + parameter WIDTHA = 4; + parameter SIZEA = 1024; + parameter ADDRWIDTHA = 10; + + parameter WIDTHB = 16; + parameter SIZEB = 256; + parameter ADDRWIDTHB = 8; + + input clkA; + input clkB; + input weA; + input enaA, enaB; + input [ADDRWIDTHA-1:0] addrA; + input [ADDRWIDTHB-1:0] addrB; + input [WIDTHA-1:0] diA; + output [WIDTHB-1:0] doB; + + `define max(a,b) {(a) > (b) ? (a) : (b)} + `define min(a,b) {(a) < (b) ? (a) : (b)} + + function integer log2; + input integer value; + reg [31:0] shifted; + integer res; + begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end + end + endfunction + + localparam maxSIZE = `max(SIZEA, SIZEB); + localparam maxWIDTH = `max(WIDTHA, WIDTHB); + localparam minWIDTH = `min(WIDTHA, WIDTHB); + + localparam RATIO = maxWIDTH / minWIDTH; + localparam log2RATIO = log2(RATIO); + + reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; + reg [WIDTHB-1:0] readB; + + always @(posedge clkA) + begin + if (enaA) begin + if (weA) + RAM[addrA] <= diA; + end + end + + always @(posedge clkB) + begin : ramread + integer i; + reg [log2RATIO-1:0] lsbaddr; + if (enaB) begin + for (i = 0; i < RATIO; i = i+1) begin + lsbaddr = i; + readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}]; + end + end + end + assign doB = readB; +endmodule
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