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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 21:48:02 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-16 21:48:02 -0800 |
| commit | 9935370ada858da56b5d61a3806768af11565a47 (patch) | |
| tree | 266092bbf791ab2d61b76ee1b63a72ebe8d2f3a3 /tests/arch/xilinx/attributes_test.ys | |
| parent | 6d4b6b1e69b2e332d512ed151398bb6bd8e3f3c7 (diff) | |
| parent | 33e6d0558500d14e6711f7fc4ded1ebdb296bcaa (diff) | |
| download | yosys-9935370ada858da56b5d61a3806768af11565a47.tar.gz yosys-9935370ada858da56b5d61a3806768af11565a47.tar.bz2 yosys-9935370ada858da56b5d61a3806768af11565a47.zip | |
Merge pull request #1521 from dh73/diego/memattr
Adding support for Xilinx memory attribute 'block' in single port mode.
Diffstat (limited to 'tests/arch/xilinx/attributes_test.ys')
| -rw-r--r-- | tests/arch/xilinx/attributes_test.ys | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys new file mode 100644 index 000000000..4c881b280 --- /dev/null +++ b/tests/arch/xilinx/attributes_test.ys @@ -0,0 +1,47 @@ +# Check that blockram memory without parameters is not modified +read_verilog ../common/memory_attributes/attributes_test.v +hierarchy -top block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Check that distributed memory without parameters is not modified +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +hierarchy -top distributed_ram +synth_xilinx -top distributed_ram +cd distributed_ram # Constrain all select calls below inside the top module +select -assert-count 8 t:RAM32X1D + +# Set ram_style distributed to blockram memory; will be implemented as distributed +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +prep +setattr -mod -set ram_style "distributed" block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 32 t:RAM128X1D + +# Set synthesis, logic_block to blockram memory; will be implemented as distributed +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +prep +setattr -mod -set logic_block 1 block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 0 t:RAMB18E1 +select -assert-count 32 t:RAM128X1D + +# Set ram_style block to a distributed memory; will be implemented as blockram +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +synth_xilinx -top distributed_ram_manual +cd distributed_ram_manual # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +synth_xilinx -top distributed_ram_manual_syn +cd distributed_ram_manual_syn # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 |