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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-12-30 20:34:31 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-30 20:34:31 +0100 |
| commit | c0a17c2457532726b05586d3b7a030bd9f372dea (patch) | |
| tree | 7db5e128665cb486880bcf7c01e08cc060a3469d /tests/arch/xilinx/attributes_test.ys | |
| parent | c2c74f9bb001bba026270a6c218fc462aeaac6c2 (diff) | |
| parent | f9749c202c93e1c9c6edb522999eacc323039b95 (diff) | |
| download | yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.tar.gz yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.tar.bz2 yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.zip | |
Merge pull request #1589 from YosysHQ/iopad_default
Make iopad option default for all xilinx flows
Diffstat (limited to 'tests/arch/xilinx/attributes_test.ys')
| -rw-r--r-- | tests/arch/xilinx/attributes_test.ys | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys index 4c881b280..7bdd94a63 100644 --- a/tests/arch/xilinx/attributes_test.ys +++ b/tests/arch/xilinx/attributes_test.ys @@ -1,7 +1,7 @@ # Check that blockram memory without parameters is not modified read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top block_ram -synth_xilinx -top block_ram +synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 @@ -9,7 +9,7 @@ select -assert-count 1 t:RAMB18E1 design -reset read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top distributed_ram -synth_xilinx -top distributed_ram +synth_xilinx -top distributed_ram -noiopad cd distributed_ram # Constrain all select calls below inside the top module select -assert-count 8 t:RAM32X1D @@ -18,7 +18,7 @@ design -reset read_verilog ../common/memory_attributes/attributes_test.v prep setattr -mod -set ram_style "distributed" block_ram -synth_xilinx -top block_ram +synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 32 t:RAM128X1D @@ -27,7 +27,7 @@ design -reset read_verilog ../common/memory_attributes/attributes_test.v prep setattr -mod -set logic_block 1 block_ram -synth_xilinx -top block_ram +synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 0 t:RAMB18E1 select -assert-count 32 t:RAM128X1D @@ -35,13 +35,13 @@ select -assert-count 32 t:RAM128X1D # Set ram_style block to a distributed memory; will be implemented as blockram design -reset read_verilog ../common/memory_attributes/attributes_test.v -synth_xilinx -top distributed_ram_manual +synth_xilinx -top distributed_ram_manual -noiopad cd distributed_ram_manual # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 # Set synthesis, ram_block block to a distributed memory; will be implemented as blockram design -reset read_verilog ../common/memory_attributes/attributes_test.v -synth_xilinx -top distributed_ram_manual_syn +synth_xilinx -top distributed_ram_manual_syn -noiopad cd distributed_ram_manual_syn # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 |