Merge branch 'master' of https://github.com/YosysHQ/yosys into abc_scratchpad_script

1 files changed, 16 insertions, 0 deletions

diff --git a/tests/arch/xilinx/bug1598.ys b/tests/arch/xilinx/bug1598.ys
new file mode 100644
index 000000000..1175380b1
--- /dev/null
+++ b/tests/arch/xilinx/bug1598.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module led_blink (
+        input clk,
+        output ledc
+    );
+ 
+    reg [6:0] led_counter = 0;
+    always @( posedge clk ) begin
+            led_counter <= led_counter + 1;
+    end
+    assign ledc = !led_counter[ 6:3 ];
+ 
+endmodule
+EOT
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9