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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 10:34:10 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 10:34:10 -0800 |
| commit | f443695a38fbdd8c2ca38cab45ca964a173dc158 (patch) | |
| tree | 4ac13e4fe8ee5e71f963c4230f9f26f32901c2ba /tests/arch/xilinx/dffs.ys | |
| parent | d730bba6d2847515795c32d3a753320b8b48bee0 (diff) | |
| parent | da6abc014987ef562a577dc374bcb03aad9256cd (diff) | |
| download | yosys-f443695a38fbdd8c2ca38cab45ca964a173dc158.tar.gz yosys-f443695a38fbdd8c2ca38cab45ca964a173dc158.tar.bz2 yosys-f443695a38fbdd8c2ca38cab45ca964a173dc158.zip | |
Merge remote-tracking branch 'origin/master' into eddie/verific_help
Diffstat (limited to 'tests/arch/xilinx/dffs.ys')
| -rw-r--r-- | tests/arch/xilinx/dffs.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys index 0bba4858f..dc764b033 100644 --- a/tests/arch/xilinx/dffs.ys +++ b/tests/arch/xilinx/dffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top dff proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDRE %% t:* %D design -load read hierarchy -top dffe proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG |