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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 11:46:56 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 11:46:56 -0800 |
| commit | 53a99ade9cbab883de5d1dcc30ad89d75266df7f (patch) | |
| tree | 17808f6ffdfdd90c44a56aaddf626d5884a821a3 /tests/arch/xilinx/fsm.ys | |
| parent | 531fddf797a79b46df3e462112ca68ff50e6a18e (diff) | |
| parent | 61ffd2d1996befd8c27c4f36f07567824bd7605e (diff) | |
| download | yosys-53a99ade9cbab883de5d1dcc30ad89d75266df7f.tar.gz yosys-53a99ade9cbab883de5d1dcc30ad89d75266df7f.tar.bz2 yosys-53a99ade9cbab883de5d1dcc30ad89d75266df7f.zip | |
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Diffstat (limited to 'tests/arch/xilinx/fsm.ys')
| -rw-r--r-- | tests/arch/xilinx/fsm.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 3235d5af3..a464fcfdb 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -9,7 +9,7 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module - +stat select -assert-count 1 t:BUFG select -assert-count 4 t:FDRE select -assert-count 1 t:FDSE |