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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
| commit | 09ee96e8c22ec692ee3ee31b8c211646eabbcf27 (patch) | |
| tree | 8b24dad9db0013ee3db20326b00941bd2abb10d1 /tests/arch/xilinx/macc.ys | |
| parent | 304e5f9ea45b8a4e2a28aba7f2820d1862377fef (diff) | |
| parent | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff) | |
| download | yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.gz yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.bz2 yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/arch/xilinx/macc.ys')
| -rw-r--r-- | tests/arch/xilinx/macc.ys | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys new file mode 100644 index 000000000..6e884b35a --- /dev/null +++ b/tests/arch/xilinx/macc.ys @@ -0,0 +1,31 @@ +read_verilog macc.v +design -save read + +hierarchy -top macc +proc +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd macc # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE +select -assert-count 1 t:DSP48E1 +select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D + +design -load read +hierarchy -top macc2 +proc +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd macc2 # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT2 +select -assert-count 41 t:LUT3 +select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D |