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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-18 12:08:38 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-18 12:08:38 -0800 |
| commit | d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a (patch) | |
| tree | 526c60c70ac41f71eb0c1a0d83f556ce1b35b126 /tests/arch/xilinx/macc.ys | |
| parent | dccd7eb39f897f7fb04b038ee8ac11e676a8ea77 (diff) | |
| parent | 520f1646cf0c0d83603c4bec2f6a37acca1d4960 (diff) | |
| download | yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.tar.gz yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.tar.bz2 yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'tests/arch/xilinx/macc.ys')
| -rw-r--r-- | tests/arch/xilinx/macc.ys | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys index 6e884b35a..11e959976 100644 --- a/tests/arch/xilinx/macc.ys +++ b/tests/arch/xilinx/macc.ys @@ -23,9 +23,10 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd macc2 # Constrain all select calls below inside the top module + select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 1 t:FDRE select -assert-count 1 t:LUT2 -select -assert-count 41 t:LUT3 +select -assert-count 40 t:LUT3 select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D |