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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 21:48:21 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-16 21:48:21 -0800 |
| commit | a73f96594f4688afc85098b485ef7788e79f5c33 (patch) | |
| tree | 8b4fdf160bcb8a8db62a309fd409096a721bb3c7 /tests/arch/xilinx/memory.ys | |
| parent | 9935370ada858da56b5d61a3806768af11565a47 (diff) | |
| parent | 5d009964266e3b52a01c72ee930601d0ebf3a838 (diff) | |
| download | yosys-a73f96594f4688afc85098b485ef7788e79f5c33.tar.gz yosys-a73f96594f4688afc85098b485ef7788e79f5c33.tar.bz2 yosys-a73f96594f4688afc85098b485ef7788e79f5c33.zip | |
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
xilinx: add LUTRAM rules for RAM32M, RAM64M
Diffstat (limited to 'tests/arch/xilinx/memory.ys')
| -rw-r--r-- | tests/arch/xilinx/memory.ys | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys deleted file mode 100644 index da1ed0e49..000000000 --- a/tests/arch/xilinx/memory.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog ../common/memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 1 t:BUFG -select -assert-count 8 t:FDRE -select -assert-count 8 t:RAM64X1D -select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D |