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authorEddie Hung <eddie@fpgeh.com>2019-11-19 15:40:39 -0800
committerEddie Hung <eddie@fpgeh.com>2019-11-19 15:40:39 -0800
commit09ee96e8c22ec692ee3ee31b8c211646eabbcf27 (patch)
tree8b24dad9db0013ee3db20326b00941bd2abb10d1 /tests/arch/xilinx/mul_unsigned.v
parent304e5f9ea45b8a4e2a28aba7f2820d1862377fef (diff)
parent7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff)
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Merge remote-tracking branch 'origin/master' into xaig_dff
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+/*
+Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89].
+*/
+
+// Unsigned 16x24-bit Multiplier
+// 1 latency stage on operands
+// 3 latency stage after the multiplication
+// File: multipliers2.v
+//
+module mul_unsigned (clk, A, B, RES);
+parameter WIDTHA = /*16*/ 6;
+parameter WIDTHB = /*24*/ 9;
+input clk;
+input [WIDTHA-1:0] A;
+input [WIDTHB-1:0] B;
+output [WIDTHA+WIDTHB-1:0] RES;
+reg [WIDTHA-1:0] rA;
+reg [WIDTHB-1:0] rB;
+reg [WIDTHA+WIDTHB-1:0] M [3:0];
+integer i;
+always @(posedge clk)
+ begin
+ rA <= A;
+ rB <= B;
+ M[0] <= rA * rB;
+ for (i = 0; i < 3; i = i+1)
+ M[i+1] <= M[i];
+ end
+assign RES = M[3];
+endmodule