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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-18 12:08:38 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-18 12:08:38 -0800 |
| commit | d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a (patch) | |
| tree | 526c60c70ac41f71eb0c1a0d83f556ce1b35b126 /tests/arch/xilinx/mux.ys | |
| parent | dccd7eb39f897f7fb04b038ee8ac11e676a8ea77 (diff) | |
| parent | 520f1646cf0c0d83603c4bec2f6a37acca1d4960 (diff) | |
| download | yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.tar.gz yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.tar.bz2 yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'tests/arch/xilinx/mux.ys')
| -rw-r--r-- | tests/arch/xilinx/mux.ys | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 821d0fab7..388272449 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -40,6 +40,8 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 5 t:LUT6 +select -assert-min 5 t:LUT6 +select -assert-max 7 t:LUT6 +select -assert-max 2 t:MUXF7 -select -assert-none t:LUT6 %% t:* %D +select -assert-none t:LUT6 t:MUXF7 %% t:* %D |