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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 10:47:31 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 10:47:31 -0800 |
| commit | b6a1f627b5871e750fe6a559fbb42334c7de8b84 (patch) | |
| tree | f1b284aebe30d0f7eabd9e8919b4275a38ff2ae4 /tests/arch/xilinx/opt_lut_ins.ys | |
| parent | 5aaa19f1ab33394accbe633cd96a3fbe281dd09a (diff) | |
| parent | 5ebdc0f8e07989b79337ced0553bd28819a8cf3e (diff) | |
| download | yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.tar.gz yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.tar.bz2 yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.zip | |
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
Diffstat (limited to 'tests/arch/xilinx/opt_lut_ins.ys')
| -rw-r--r-- | tests/arch/xilinx/opt_lut_ins.ys | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/arch/xilinx/opt_lut_ins.ys b/tests/arch/xilinx/opt_lut_ins.ys new file mode 100644 index 000000000..a01d02179 --- /dev/null +++ b/tests/arch/xilinx/opt_lut_ins.ys @@ -0,0 +1,25 @@ +read_ilang << EOF + +module \top + + wire width 4 input 1 \A + + wire output 2 \O + + cell \LUT4 $0 + parameter \INIT 16'1111110011000000 + connect \I0 \A [0] + connect \I1 \A [1] + connect \I2 \A [2] + connect \I3 \A [3] + connect \O \O + end +end + +EOF + +equiv_opt -assert -map +/xilinx/cells_sim.v opt_lut_ins -tech xilinx + +design -load postopt + +select -assert-count 1 t:LUT3 |