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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-17 19:25:59 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-17 19:25:59 -0800 |
| commit | 67c6bf0b6b8a5a2d03a7e64b3baa5c1d3021e6d1 (patch) | |
| tree | 10fadff3585ad4c56a2a0fcefcf44f9e6e36eefe /tests/arch/xilinx/xilinx_dsp.ys | |
| parent | 2bda51ac34d6f542d1d6477eecede1d6527c10b3 (diff) | |
| parent | 6a163b5ddd378ba847054ad9226af8ca569c977a (diff) | |
| download | yosys-67c6bf0b6b8a5a2d03a7e64b3baa5c1d3021e6d1.tar.gz yosys-67c6bf0b6b8a5a2d03a7e64b3baa5c1d3021e6d1.tar.bz2 yosys-67c6bf0b6b8a5a2d03a7e64b3baa5c1d3021e6d1.zip | |
Merge pull request #1645 from YosysHQ/eddie/fix1644
{ice40,xilinx}_dsp: improve robustess
Diffstat (limited to 'tests/arch/xilinx/xilinx_dsp.ys')
| -rw-r--r-- | tests/arch/xilinx/xilinx_dsp.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys new file mode 100644 index 000000000..3b9f52930 --- /dev/null +++ b/tests/arch/xilinx/xilinx_dsp.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module top(input [24:0] a, input [17:0] b, output [42:0] o1, o2, o5); +DSP48E1 m1 (.A(a), .B(16'd1234), .P(o1)); +assign o2 = a * 16'd0; +wire [42:0] o3, o4; +DSP48E1 m2 (.A(a), .B(b), .P(o3)); +assign o4 = a * b; +DSP48E1 m3 (.A(a), .B(b), .P(o5)); +endmodule +EOT +xilinx_dsp |