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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-11-09 11:22:48 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-11-09 15:40:16 +0100 |
| commit | 15b0d717ed658b342ce5f74df5a65827eed04a94 (patch) | |
| tree | e9dfb025526ea0f1fbddf705987872fc889a951c /tests/arch | |
| parent | 4871d8f19911dc48bf7726519437be8a821c0a1f (diff) | |
| download | yosys-15b0d717ed658b342ce5f74df5a65827eed04a94.tar.gz yosys-15b0d717ed658b342ce5f74df5a65827eed04a94.tar.bz2 yosys-15b0d717ed658b342ce5f74df5a65827eed04a94.zip | |
iopadmap: Add native support for negative-polarity output enable.
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/machxo2/mux.ys | 2 | ||||
| -rw-r--r-- | tests/arch/machxo2/tribuf.ys | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys index 6c8aa857c..7b7e62d4c 100644 --- a/tests/arch/machxo2/mux.ys +++ b/tests/arch/machxo2/mux.ys @@ -35,6 +35,6 @@ proc equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 11 t:LUT4 +select -assert-max 12 t:LUT4 select -assert-none t:LUT4 t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys index 9c00a8bcf..fce342e18 100644 --- a/tests/arch/machxo2/tribuf.ys +++ b/tests/arch/machxo2/tribuf.ys @@ -6,5 +6,5 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module select -assert-count 3 t:FACADE_IO -select -assert-count 1 t:$not -select -assert-none t:FACADE_IO t:$not %% t:* %D +select -assert-count 1 t:LUT4 +select -assert-none t:FACADE_IO t:LUT4 %% t:* %D |