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| author | Diego H <diego@symbioticeda.com> | 2019-12-12 16:06:46 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-12-12 16:06:46 -0600 |
| commit | e33f407655fa516cb2f6754103973eb156ca90cf (patch) | |
| tree | 2378f7170d386aaadfa0b5e30d8d270bd887faf3 /tests/arch | |
| parent | 937ec1ee78e5470c148d8c39387c7a80711af8a7 (diff) | |
| download | yosys-e33f407655fa516cb2f6754103973eb156ca90cf.tar.gz yosys-e33f407655fa516cb2f6754103973eb156ca90cf.tar.bz2 yosys-e33f407655fa516cb2f6754103973eb156ca90cf.zip | |
Adding a note (TODO) in the memory_params.ys check file
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/xilinx/memory_params.ys | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys index f279a4a6e..657629e0f 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/memory_params.ys @@ -1,3 +1,5 @@ +## TODO: Not running equivalence checking because BRAM models does not exists +## currently. Checking instance counts instead. # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 read_verilog ../common/memory_params.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp |