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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-06 23:04:04 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-06 23:04:04 -0800 |
| commit | ecb0c68f0751b3bd97f8da94e7bd2258987d58e1 (patch) | |
| tree | edea0635c2cae9a0b84a46f4e9eb4ac31079381a /tests/arch | |
| parent | 7dece7955e9682dddec67eb99d4f99742e637a07 (diff) | |
| parent | dcb30b5f4a49379a41fe4e279526b93da31eeabd (diff) | |
| download | yosys-ecb0c68f0751b3bd97f8da94e7bd2258987d58e1.tar.gz yosys-ecb0c68f0751b3bd97f8da94e7bd2258987d58e1.tar.bz2 yosys-ecb0c68f0751b3bd97f8da94e7bd2258987d58e1.zip | |
Merge pull request #1555 from antmicro/fix-macc-xilinx-test
tests: arch: xilinx: Change order of arguments in macc.sh
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/xilinx/macc.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/xilinx/macc.sh b/tests/arch/xilinx/macc.sh index 2272679ee..154a29848 100644 --- a/tests/arch/xilinx/macc.sh +++ b/tests/arch/xilinx/macc.sh @@ -1,3 +1,3 @@ -../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v +../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v vvp -N ./test_macc |