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authorClifford Wolf <clifford@clifford.at>2015-02-12 17:45:44 +0100
committerClifford Wolf <clifford@clifford.at>2015-02-12 17:45:44 +0100
commitd58c3eca3a6d4ab00021769fb31ee0279c2fcbab (patch)
tree20d893fe76bc6b392e672f414720fc67295a6fdc /tests/asicworld/code_hdl_models_dlatch_reset.v
parent554a8df5e2e7c750b76021821bdf2e07970b9dbf (diff)
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Some test related fixes
(incl. removal of three bad test cases)
Diffstat (limited to 'tests/asicworld/code_hdl_models_dlatch_reset.v')
-rw-r--r--tests/asicworld/code_hdl_models_dlatch_reset.v30
1 files changed, 0 insertions, 30 deletions
diff --git a/tests/asicworld/code_hdl_models_dlatch_reset.v b/tests/asicworld/code_hdl_models_dlatch_reset.v
deleted file mode 100644
index 2cfc6fbd8..000000000
--- a/tests/asicworld/code_hdl_models_dlatch_reset.v
+++ /dev/null
@@ -1,30 +0,0 @@
-//-----------------------------------------------------
-// Design Name : dlatch_reset
-// File Name : dlatch_reset.v
-// Function : DLATCH async reset
-// Coder : Deepak Kumar Tala
-//-----------------------------------------------------
-module dlatch_reset (
-data , // Data Input
-en , // LatchInput
-reset , // Reset input
-q // Q output
-);
-//-----------Input Ports---------------
-input data, en, reset ;
-
-//-----------Output Ports---------------
-output q;
-
-//------------Internal Variables--------
-reg q;
-
-//-------------Code Starts Here---------
-always @ ( en or reset or data)
-if (~reset) begin
- q <= 1'b0;
-end else if (en) begin
- q <= data;
-end
-
-endmodule //End Of Module dlatch_reset