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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-27 09:17:29 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-01-27 09:17:29 +0100 |
| commit | bf798a9020f1a8281f42f7f69d8d05d9e75114cb (patch) | |
| tree | a49ee1e10803ba30cb29582790ff699663e6e632 /tests/asicworld/code_hdl_models_misc1.v | |
| parent | c82aa49d9efa81c1e6c6e2d1a7507e3155d279e3 (diff) | |
| parent | 9666cca9ddba2e6d242006e80d66277b8b4df0fd (diff) | |
| download | yosys-bf798a9020f1a8281f42f7f69d8d05d9e75114cb.tar.gz yosys-bf798a9020f1a8281f42f7f69d8d05d9e75114cb.tar.bz2 yosys-bf798a9020f1a8281f42f7f69d8d05d9e75114cb.zip | |
Merge branch 'whitequark-write_verilog_keyword'
Diffstat (limited to 'tests/asicworld/code_hdl_models_misc1.v')
| -rw-r--r-- | tests/asicworld/code_hdl_models_misc1.v | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/tests/asicworld/code_hdl_models_misc1.v b/tests/asicworld/code_hdl_models_misc1.v deleted file mode 100644 index e3d9d5d64..000000000 --- a/tests/asicworld/code_hdl_models_misc1.v +++ /dev/null @@ -1,22 +0,0 @@ -module misc1 (a,b,c,d,y); -input a, b,c,d; -output y; - -wire net1,net2,net3; - -supply1 vdd; -supply0 vss; - -// y = !((a+b+c).d) - -pmos p1 (vdd,net1,a); -pmos p2 (net1,net2,b); -pmos p3 (net2,y,c); -pmos p4 (vdd,y,d); - -nmos n1 (vss,net3,a); -nmos n2 (vss,net3,b); -nmos n3 (vss,net3,c); -nmos n4 (net3,y,d); - -endmodule |