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| author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
| commit | 7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch) | |
| tree | 18c05b8729df381af71b707748ce1d605e0df764 /tests/asicworld/code_hdl_models_nand_switch.v | |
| download | yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.gz yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.bz2 yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.zip | |
initial import
Diffstat (limited to 'tests/asicworld/code_hdl_models_nand_switch.v')
| -rw-r--r-- | tests/asicworld/code_hdl_models_nand_switch.v | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/asicworld/code_hdl_models_nand_switch.v b/tests/asicworld/code_hdl_models_nand_switch.v new file mode 100644 index 000000000..1ccdd3a7c --- /dev/null +++ b/tests/asicworld/code_hdl_models_nand_switch.v @@ -0,0 +1,14 @@ +module nand_switch(a,b,out); +input a,b; +output out; + +supply0 vss; +supply1 vdd; +wire net1; + +pmos p1 (vdd,out,a); +pmos p2 (vdd,out,b); +nmos n1 (vss,net1,a); +nmos n2 (net1,out,b); + +endmodule
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