initial import

1 files changed, 19 insertions, 0 deletions

diff --git a/tests/asicworld/code_tidbits_syn_reset.v b/tests/asicworld/code_tidbits_syn_reset.v
new file mode 100644
index 000000000..994771b16
--- /dev/null
+++ b/tests/asicworld/code_tidbits_syn_reset.v
@@ -0,0 +1,19 @@
+module syn_reset (clk,reset,a,c);
+   input clk;
+   input reset;
+   input a; 
+   output c; 
+
+   wire clk;
+   wire reset;   
+   wire a;   
+   reg c;
+  
+always @ (posedge clk )
+  if ( reset == 1'b1) begin
+    c <= 0;
+  end else begin
+    c <= a;
+  end
+ 
+endmodule