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| author | Claire Wolf <claire@symbioticeda.com> | 2020-04-22 14:51:20 +0200 |
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| committer | Claire Wolf <claire@symbioticeda.com> | 2020-04-22 14:51:20 +0200 |
| commit | 9f1fb11b1d4d7326c4ba543778993dd6fb655953 (patch) | |
| tree | 11e8419db64f2144e0e43b000d11d7cb912fcfa7 /tests/asicworld/code_tidbits_syn_reset.v | |
| parent | 02f1c7b9afd1d35964245ea045db8642d8da3d14 (diff) | |
| download | yosys-9f1fb11b1d4d7326c4ba543778993dd6fb655953.tar.gz yosys-9f1fb11b1d4d7326c4ba543778993dd6fb655953.tar.bz2 yosys-9f1fb11b1d4d7326c4ba543778993dd6fb655953.zip | |
Clear current_scope when done with RTLIL generation, fixes #1837
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Diffstat (limited to 'tests/asicworld/code_tidbits_syn_reset.v')
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