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author	Eddie Hung <eddie@fpgeh.com>	2019-12-01 23:19:32 -0800
committer	Eddie Hung <eddie@fpgeh.com>	2019-12-01 23:19:32 -0800
commit	4ac1b92df33d1ef4bbed71216e2b39c4a0651e5b (patch)
tree	ad228abd3fa30f1367f8a7856fd44b1bd74d81dd /tests/asicworld/code_verilog_tutorial_addbit.v
parent	b1ab7c16c41f0a14b8b14a041367f2259b3c0e37 (diff)
download	yosys-4ac1b92df33d1ef4bbed71216e2b39c4a0651e5b.tar.gz yosys-4ac1b92df33d1ef4bbed71216e2b39c4a0651e5b.tar.bz2 yosys-4ac1b92df33d1ef4bbed71216e2b39c4a0651e5b.zip

Use pool<> not std::set<> for determinism

Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_addbit.v')

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From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Thu, 1 Oct 2015 20:27:19 +0100
Subject: [PATCH] phylink: add ethtool nway_reset support

Add ethtool nway_reset support to phylink, to allow userspace to
request a re-negotiation of the link.

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---

--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -783,6 +783,20 @@ int phylink_ethtool_ksettings_set(struct
 }
 EXPORT_SYMBOL_GPL(phylink_ethtool_ksettings_set);
 
+int phylink_ethtool_nway_reset(struct phylink *pl)
+{
+	int ret = 0;
+
+	mutex_lock(&pl->config_mutex);
+	if (pl->phydev)
+		ret = genphy_restart_aneg(pl->phydev);
+	phylink_mac_an_restart(pl);
+	mutex_unlock(&pl->config_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(phylink_ethtool_nway_reset);
+
 /* This emulates MII registers for a fixed-mode phy operating as per the
  * passed in state. "aneg" defines if we report negotiation is possible.
  *
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -86,6 +86,7 @@ int phylink_ethtool_ksettings_get(struct
 				  struct ethtool_link_ksettings *);
 int phylink_ethtool_ksettings_set(struct phylink *,
 				  const struct ethtool_link_ksettings *);
+int phylink_ethtool_nway_reset(struct phylink *);
 int phylink_mii_ioctl(struct phylink *, struct ifreq *, int);
 
 int phylink_set_link(struct phylink *pl, unsigned int mode, u8 port,


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