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| author | Ethan Mahintorabi <ethanmoon@google.com> | 2020-10-28 18:59:59 -0700 |
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| committer | Ethan Mahintorabi <ethanmoon@google.com> | 2020-10-28 19:00:06 -0700 |
| commit | 5c36e7757c4a65c7dc32509534501bda4fb5e35e (patch) | |
| tree | c5a3cba20270482867c1322eec4d7835cbc6e013 /tests/asicworld/code_verilog_tutorial_addbit.v | |
| parent | e2a39bb1e71b97d423a3c2233abce996376e25dd (diff) | |
| download | yosys-5c36e7757c4a65c7dc32509534501bda4fb5e35e.tar.gz yosys-5c36e7757c4a65c7dc32509534501bda4fb5e35e.tar.bz2 yosys-5c36e7757c4a65c7dc32509534501bda4fb5e35e.zip | |
This patch adds support for defining the ABC location at runtime instead of at compile time. This is helpful in build systems like bazel which do not have stable locations for binaries or directories during the compilation phase.
This change should be backwards compatible with the existing behavior.
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_addbit.v')
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