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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-24 13:27:04 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-24 13:27:11 +0100 |
| commit | bbae24bdf7dc241db25a29efbd06f7c70517258c (patch) | |
| tree | 7aa7054367fd507950b8f888d5111cf52c4f2932 /tests/asicworld/code_verilog_tutorial_addbit.v | |
| parent | f921b06fb05b9b776a70f161bf09c421907dec99 (diff) | |
| download | yosys-bbae24bdf7dc241db25a29efbd06f7c70517258c.tar.gz yosys-bbae24bdf7dc241db25a29efbd06f7c70517258c.tar.bz2 yosys-bbae24bdf7dc241db25a29efbd06f7c70517258c.zip | |
Added show -strech and renamed -widthlabels to -width
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_addbit.v')
0 files changed, 0 insertions, 0 deletions