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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-26 09:22:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-13 19:11:23 -0700 |
| commit | 0808318d55a4ac6ccb374393ab73c3b2bb27be6d (patch) | |
| tree | 49df6a2c5b6621db1931ea128fe9435036a3dbc8 /tests/asicworld/code_verilog_tutorial_counter.v | |
| parent | 840bb170896c1acbbd321c4214df1f3b15108466 (diff) | |
| download | yosys-0808318d55a4ac6ccb374393ab73c3b2bb27be6d.tar.gz yosys-0808318d55a4ac6ccb374393ab73c3b2bb27be6d.tar.bz2 yosys-0808318d55a4ac6ccb374393ab73c3b2bb27be6d.zip | |
xaiger: add check for $__ABC9_DELAY model
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_counter.v')
0 files changed, 0 insertions, 0 deletions