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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-31 15:28:57 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2018-10-31 15:28:57 +0100 |
| commit | cf79fd43761b6501f392ee6ad4ed0f961b93a56f (patch) | |
| tree | 63e8b916f2e2d6da1d69630c10c714b6b4899808 /tests/asicworld/code_verilog_tutorial_decoder.v | |
| parent | db676957a0c3032ff44e3195d770948c1c3660af (diff) | |
| download | yosys-cf79fd43761b6501f392ee6ad4ed0f961b93a56f.tar.gz yosys-cf79fd43761b6501f392ee6ad4ed0f961b93a56f.tar.bz2 yosys-cf79fd43761b6501f392ee6ad4ed0f961b93a56f.zip | |
Basic SmartFusion2 and IGLOO2 synthesis support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_decoder.v')
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