diff options
| author | Clifford Wolf <clifford@clifford.at> | 2017-08-18 11:44:50 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-08-18 11:44:50 +0200 |
| commit | d30cc60ba9148346173a1ed26f0ce833de522003 (patch) | |
| tree | e13bef6ed28f4ac4efa764b58c9454a54c3e702e /tests/asicworld/code_verilog_tutorial_parity.v | |
| parent | 4ba5bd12c612cbe27422cf86fe317d0723b11f30 (diff) | |
| download | yosys-d30cc60ba9148346173a1ed26f0ce833de522003.tar.gz yosys-d30cc60ba9148346173a1ed26f0ce833de522003.tar.bz2 yosys-d30cc60ba9148346173a1ed26f0ce833de522003.zip | |
Add "sim" support for memories
Diffstat (limited to 'tests/asicworld/code_verilog_tutorial_parity.v')
0 files changed, 0 insertions, 0 deletions