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| author | luke whittlesey <luke.whittlesey@gmail.com> | 2015-06-04 14:56:13 -0400 |
|---|---|---|
| committer | luke whittlesey <luke.whittlesey@gmail.com> | 2015-06-04 16:12:40 -0400 |
| commit | a8fe0409062cb214d61d527ad2060c1f3d585026 (patch) | |
| tree | ccbe8e333f8f9b7e52aeb0eae09cd9bcf5c5a2ac /tests/bram/run-single.sh | |
| parent | 08f9b38a9c974318efa071cd78616b1bc8de73b3 (diff) | |
| download | yosys-a8fe0409062cb214d61d527ad2060c1f3d585026.tar.gz yosys-a8fe0409062cb214d61d527ad2060c1f3d585026.tar.bz2 yosys-a8fe0409062cb214d61d527ad2060c1f3d585026.zip | |
Bug fix in $mem verilog backend + changed tests/bram flow of make test.
Diffstat (limited to 'tests/bram/run-single.sh')
| -rw-r--r-- | tests/bram/run-single.sh | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index 19a235c7a..a1d1ec908 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -1,7 +1,9 @@ #!/bin/bash set -e -../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ - -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v +../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full; write_verilog temp/synth_${1}_${2}_stage0.v" \ + -l temp/synth_${1}_${2}_stage0.log temp/brams_${1}.v +../../yosys -qq -p "proc; opt; memory -nomap; opt -fast -full; write_verilog -nomem temp/synth_${1}_${2}.v" \ + -l temp/synth_${1}_${2}.log temp/synth_${1}_${2}_stage0.v iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1ns -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt |