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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-03 11:53:37 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-03 11:53:37 +0300 |
| commit | 11f330ed223f524cbbdbe2433599990a69b8f380 (patch) | |
| tree | 627373ced7ca850efe284caf31c7866cddaa934b /tests/ecp5/macc.ys | |
| parent | 7e8f7f4c59c96897159d32771d0c7179c5474281 (diff) | |
| download | yosys-11f330ed223f524cbbdbe2433599990a69b8f380.tar.gz yosys-11f330ed223f524cbbdbe2433599990a69b8f380.tar.bz2 yosys-11f330ed223f524cbbdbe2433599990a69b8f380.zip | |
Add tests for ECP5 architecture
Diffstat (limited to 'tests/ecp5/macc.ys')
| -rw-r--r-- | tests/ecp5/macc.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys new file mode 100644 index 000000000..bc6340509 --- /dev/null +++ b/tests/ecp5/macc.ys @@ -0,0 +1,15 @@ +read_verilog macc.v +proc +hierarchy -top top +#Failed because of 14 unproven cells. +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +#equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:CCU2C +select -assert-count 6 t:L6MUX21 +select -assert-count 49 t:LUT4 +select -assert-count 19 t:PFUMX +select -assert-count 7 t:TRELLIS_FF + +select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D |