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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-27 18:28:05 +0300 |
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| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-27 18:28:05 +0300 |
| commit | 980830f7b82f2a974f43580f61e917f99fbb4e7e (patch) | |
| tree | ef4b9cfe86945794171527976315924faf99e157 /tests/ecp5/memory.v | |
| parent | 134d3fea909bae02f4f814e3d649658502b44b73 (diff) | |
| download | yosys-980830f7b82f2a974f43580f61e917f99fbb4e7e.tar.gz yosys-980830f7b82f2a974f43580f61e917f99fbb4e7e.tar.bz2 yosys-980830f7b82f2a974f43580f61e917f99fbb4e7e.zip | |
Revert "Add tests for ecp5 architecture."
This reverts commit 134d3fea909bae02f4f814e3d649658502b44b73.
Diffstat (limited to 'tests/ecp5/memory.v')
| -rw-r--r-- | tests/ecp5/memory.v | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/ecp5/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule |