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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 12:20:49 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 12:20:49 +0200 |
| commit | ef417fb1b3555a3075bcd01cb7c5267f3e55b407 (patch) | |
| tree | 80813ffc49a6a645cb28224af9359ebfe12634a5 /tests/efinix/logic.v | |
| parent | 2ed2e9c3e8f2d9d6882588857c8556a6e2af57ea (diff) | |
| parent | eb750670e3835a1bad36cb604e04bf4836cc7f91 (diff) | |
| download | yosys-ef417fb1b3555a3075bcd01cb7c5267f3e55b407.tar.gz yosys-ef417fb1b3555a3075bcd01cb7c5267f3e55b407.tar.bz2 yosys-ef417fb1b3555a3075bcd01cb7c5267f3e55b407.zip | |
Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix
Diffstat (limited to 'tests/efinix/logic.v')
| -rw-r--r-- | tests/efinix/logic.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/efinix/logic.v b/tests/efinix/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/efinix/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule |