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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-25 13:18:59 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-25 13:18:59 +0200 |
| commit | 6cd5b8b76ba9f9df04571defa33fc862aec87924 (patch) | |
| tree | 16cdd1c333ac25625713c0941ddc3fceb0354efa /tests/errors/syntax_err07.v | |
| parent | 7703be045a0a46ed70ec19b5db731e33fa56cef5 (diff) | |
| parent | 536ae16c3abcf3fef1dd14df8733bf51fa1bce1a (diff) | |
| download | yosys-6cd5b8b76ba9f9df04571defa33fc862aec87924.tar.gz yosys-6cd5b8b76ba9f9df04571defa33fc862aec87924.tar.bz2 yosys-6cd5b8b76ba9f9df04571defa33fc862aec87924.zip | |
Merge pull request #679 from udif/pr_syntax_error
More meaningful SystemVerilog/Verilog parser error messages
Diffstat (limited to 'tests/errors/syntax_err07.v')
| -rw-r--r-- | tests/errors/syntax_err07.v | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tests/errors/syntax_err07.v b/tests/errors/syntax_err07.v new file mode 100644 index 000000000..62bcc6b3e --- /dev/null +++ b/tests/errors/syntax_err07.v @@ -0,0 +1,6 @@ +module a; +wire [5:0]x; +wire [3:0]y; +assign y = (4)55; +endmodule + |