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| author | Udi Finkelstein <github@udifink.com> | 2018-10-25 02:37:56 +0300 |
|---|---|---|
| committer | Udi Finkelstein <github@udifink.com> | 2018-10-25 02:37:56 +0300 |
| commit | 536ae16c3abcf3fef1dd14df8733bf51fa1bce1a (patch) | |
| tree | 00838e80593c2d0a8d46c1b448a44ddd62a4c796 /tests/errors/syntax_err08.v | |
| parent | 11c8a9eb960fdb0a412fabcfbe787cbf5cc3a67d (diff) | |
| download | yosys-536ae16c3abcf3fef1dd14df8733bf51fa1bce1a.tar.gz yosys-536ae16c3abcf3fef1dd14df8733bf51fa1bce1a.tar.bz2 yosys-536ae16c3abcf3fef1dd14df8733bf51fa1bce1a.zip | |
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
Diffstat (limited to 'tests/errors/syntax_err08.v')
| -rw-r--r-- | tests/errors/syntax_err08.v | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tests/errors/syntax_err08.v b/tests/errors/syntax_err08.v new file mode 100644 index 000000000..d41bfd6c9 --- /dev/null +++ b/tests/errors/syntax_err08.v @@ -0,0 +1,6 @@ +module a; +wire [5:0]x; +wire [3:0]y; +assign y = x 55; +endmodule + |