diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-10-19 13:03:38 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-19 13:03:38 +0200 |
| commit | 2a104b29fd7e504bdedb27c286cf9125d46dfd55 (patch) | |
| tree | 9a0ef937b730d4c0f7452b0ceedfb642c83908ab /tests/errors/syntax_err11.v | |
| parent | a25f370191707def4d50dd42e74dec4d097a6a22 (diff) | |
| parent | d5aac2650f9169b2b890854083c5502b84adf115 (diff) | |
| download | yosys-2a104b29fd7e504bdedb27c286cf9125d46dfd55.tar.gz yosys-2a104b29fd7e504bdedb27c286cf9125d46dfd55.tar.bz2 yosys-2a104b29fd7e504bdedb27c286cf9125d46dfd55.zip | |
Merge pull request #670 from rubund/feature/basic_svinterface_test
Basic test for checking correct synthesis of SystemVerilog interfaces
Diffstat (limited to 'tests/errors/syntax_err11.v')
0 files changed, 0 insertions, 0 deletions