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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-01 03:57:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-01 03:57:37 +0200 |
| commit | 5e641acc905a5c99d037378f6b7a481c43eb7de0 (patch) | |
| tree | 9b2ab0d52d0e6469ee42132872f88f6d524f08c2 /tests/hana/test_parser.v | |
| parent | 03ef9a75c64f79596d6c931a1401184c33f9346b (diff) | |
| download | yosys-5e641acc905a5c99d037378f6b7a481c43eb7de0.tar.gz yosys-5e641acc905a5c99d037378f6b7a481c43eb7de0.tar.bz2 yosys-5e641acc905a5c99d037378f6b7a481c43eb7de0.zip | |
Consolidated hana test benches into fewer files
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;
..etc..
Diffstat (limited to 'tests/hana/test_parser.v')
| -rw-r--r-- | tests/hana/test_parser.v | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/tests/hana/test_parser.v b/tests/hana/test_parser.v new file mode 100644 index 000000000..c7305356a --- /dev/null +++ b/tests/hana/test_parser.v @@ -0,0 +1,87 @@ + +// test_parser_constructs_module_basic1_test.v +module f1_test; +endmodule + +// test_parser_constructs_param_basic0_test.v +module f2_test #( parameter v2kparam = 5) +(in, out, io, vin, vout, vio); +input in; +output out; +inout io; +input [3:0] vin; +output [v2kparam:0] vout; +inout [0:3] vio; +parameter myparam = 10; +endmodule + +// test_parser_constructs_port_basic0_test.v +module f3_test(in, out, io, vin, vout, vio); +input in; +output out; +inout io; +input [3:0] vin; +output [3:0] vout; +inout [0:3] vio; +endmodule + +// test_parser_directives_define_simpledef_test.v +`define parvez ahmad +`define WIRE wire +`define TEN 10 + +module f4_`parvez(); +parameter param = `TEN; +`WIRE w; +assign w = `TEN; +endmodule + +// test_parser_misc_operators_test.v +module f5_test(out, i0, i1, i2, i3, s1, s0); +output out; +input i0, i1, i2, i3; +input s1, s0; + +assign out = (~s1 & s0 & i0) | + (~s1 & s0 & i1) | + (s1 & ~s0 & i2) | + (s1 & s0 & i3); + +endmodule + +module f5_ternaryop(out, i0, i1, i2, i3, s1, s0); +output out; +input i0, i1, i2, i3; +input s1, s0; + +assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0); + +endmodule + +module f5_fulladd4(sum, c_out, a, b, c_in); +output [3:0] sum; +output c_out; +input [3:0] a, b; +input c_in; + +assign {c_out, sum} = a + b + c_in; +endmodule + +// test_parser_v2k_comb_port_data_type_test.v +module f6_adder(sum , co, a, b, ci); +output reg [31:0] sum; +output reg co; +input wire [31:0] a, b; +input wire ci; +endmodule + +// test_parser_v2k_comma_sep_sens_list_test.v +module f7_test(q, d, clk, reset); +output reg q; +input d, clk, reset; + +always @ (posedge clk, negedge reset) + if(!reset) q <= 0; + else q <= d; + +endmodule |