Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 30 insertions, 0 deletions

diff --git a/tests/hana/test_simulation_or.v b/tests/hana/test_simulation_or.v
new file mode 100644
index 000000000..9217db808
--- /dev/null
+++ b/tests/hana/test_simulation_or.v
@@ -0,0 +1,30 @@
+
+// test_simulation_or_1_test.v
+module f1_test(input [1:0] in, output out);
+assign out = in[0] | in[1];
+endmodule
+
+// test_simulation_or_2_test.v
+module f2_test(input [1:0] in, output out);
+assign out = in[0] || in[1];
+endmodule
+
+// test_simulation_or_3_test.v
+module f3_test(input [2:0] in, output out);
+assign out = in[0] | in[1] | in[2];
+endmodule
+
+// test_simulation_or_4_test.v
+module f4_test(input [2:0] in, output out);
+assign out = in[0] || in[1] || in[2];
+endmodule
+
+// test_simulation_or_5_test.v
+module f5_test(input [3:0] in, output out);
+assign out = in[0] | in[1] | in[2] | in[3];
+endmodule
+
+// test_simulation_or_6_test.v
+module f6_test(input [3:0] in, output out);
+assign out = in[0] || in[1] || in[2] || in[3];
+endmodule