Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 12 insertions, 0 deletions

diff --git a/tests/hana/test_simulation_seq.v b/tests/hana/test_simulation_seq.v
new file mode 100644
index 000000000..eba4e88ea
--- /dev/null
+++ b/tests/hana/test_simulation_seq.v
@@ -0,0 +1,12 @@
+
+// test_simulation_seq_ff_1_test.v
+module f1_test(input in,  input clk, output reg out);
+always @(posedge clk)
+    out <= in;
+endmodule	
+
+// test_simulation_seq_ff_2_test.v
+module f2_test(input  in,  input clk,  output reg out);
+always @(negedge clk)
+   out <= in;
+endmodule