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author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-24 14:55:32 +0300 |
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committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-24 14:55:32 +0300 |
commit | fc6ebf8268780c47b503e68be4b2ec368388e2c5 (patch) | |
tree | 29942096f9f393f77b0c2b510be2c1936fe6179b /tests/ice40/adffs.v | |
parent | 7e8f7f4c59c96897159d32771d0c7179c5474281 (diff) | |
download | yosys-fc6ebf8268780c47b503e68be4b2ec368388e2c5.tar.gz yosys-fc6ebf8268780c47b503e68be4b2ec368388e2c5.tar.bz2 yosys-fc6ebf8268780c47b503e68be4b2ec368388e2c5.zip |
adffs test update (equiv_opt -multiclock).
Diffstat (limited to 'tests/ice40/adffs.v')
-rw-r--r-- | tests/ice40/adffs.v | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index 93c8bf52c..05e68caf7 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -22,30 +22,26 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) + always @( negedge clk ) if ( !clr ) q <= 1'b0; - else if ( !pre ) - q <= 1'b1; else q <= d; endmodule @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), |