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author | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
commit | 09ee96e8c22ec692ee3ee31b8c211646eabbcf27 (patch) | |
tree | 8b24dad9db0013ee3db20326b00941bd2abb10d1 /tests/ice40/dpram.ys | |
parent | 304e5f9ea45b8a4e2a28aba7f2820d1862377fef (diff) | |
parent | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff) | |
download | yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.gz yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.bz2 yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.zip |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/ice40/dpram.ys')
-rw-r--r-- | tests/ice40/dpram.ys | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/tests/ice40/dpram.ys b/tests/ice40/dpram.ys deleted file mode 100644 index 4f6a253ea..000000000 --- a/tests/ice40/dpram.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog dpram.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 1 t:SB_RAM40_4K -select -assert-none t:SB_RAM40_4K %% t:* %D |