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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 10:54:22 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-30 10:54:22 -0700 |
| commit | eef0676105ff592e0e96bb835f0139f2f40d55bb (patch) | |
| tree | 6fc8cae6410a5977c16b98643c82e3d661fc0271 /tests/ice40/dpram.ys | |
| parent | 36e38ed46ae4b24be7b627a21a6627437db1ec61 (diff) | |
| parent | 53912ad649d6e9f447b9e4037255606783a0cf51 (diff) | |
| download | yosys-eef0676105ff592e0e96bb835f0139f2f40d55bb.tar.gz yosys-eef0676105ff592e0e96bb835f0139f2f40d55bb.tar.bz2 yosys-eef0676105ff592e0e96bb835f0139f2f40d55bb.zip | |
Merge pull request #1310 from SergeyDegtyar/master
Add new tests for ice40 architecture
Diffstat (limited to 'tests/ice40/dpram.ys')
| -rw-r--r-- | tests/ice40/dpram.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/ice40/dpram.ys b/tests/ice40/dpram.ys new file mode 100644 index 000000000..4f6a253ea --- /dev/null +++ b/tests/ice40/dpram.ys @@ -0,0 +1,15 @@ +read_verilog dpram.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:SB_RAM40_4K +select -assert-none t:SB_RAM40_4K %% t:* %D |