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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
| commit | 09ee96e8c22ec692ee3ee31b8c211646eabbcf27 (patch) | |
| tree | 8b24dad9db0013ee3db20326b00941bd2abb10d1 /tests/ice40/mul.ys | |
| parent | 304e5f9ea45b8a4e2a28aba7f2820d1862377fef (diff) | |
| parent | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff) | |
| download | yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.gz yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.bz2 yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/ice40/mul.ys')
| -rw-r--r-- | tests/ice40/mul.ys | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys deleted file mode 100644 index 8a0822a84..000000000 --- a/tests/ice40/mul.ys +++ /dev/null @@ -1,7 +0,0 @@ -read_verilog mul.v -hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_MAC16 -select -assert-none t:SB_MAC16 %% t:* %D |