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authorEddie Hung <eddie@fpgeh.com>2019-10-08 13:03:06 -0700
committerEddie Hung <eddie@fpgeh.com>2019-10-08 13:03:06 -0700
commit304e5f9ea45b8a4e2a28aba7f2820d1862377fef (patch)
treebe1d59d00acdcab765a2f2d43117a640d79a6d03 /tests/ice40
parent4f0818275fe44c451be59235616061be8ff5e382 (diff)
parent3fb604c75d3e8ee45d35fac8b787cb95a8adcf84 (diff)
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Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/ice40')
-rw-r--r--tests/ice40/latches.ys9
-rw-r--r--tests/ice40/wrapcarry.ys22
2 files changed, 25 insertions, 6 deletions
diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys
index f3562559e..708734e44 100644
--- a/tests/ice40/latches.ys
+++ b/tests/ice40/latches.ys
@@ -1,14 +1,11 @@
read_verilog latches.v
-design -save read
proc
-async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
flatten
-synth_ice40
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+# Can't run any sort of equivalence check because latches are blown to LUTs
+#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load read
+#design -load preopt
synth_ice40
cd top
select -assert-count 4 t:SB_LUT4
diff --git a/tests/ice40/wrapcarry.ys b/tests/ice40/wrapcarry.ys
new file mode 100644
index 000000000..10c029e68
--- /dev/null
+++ b/tests/ice40/wrapcarry.ys
@@ -0,0 +1,22 @@
+read_verilog <<EOT
+module top(input A, B, CI, output O, CO);
+ SB_CARRY carry (
+ .I0(A),
+ .I1(B),
+ .CI(CI),
+ .CO(CO)
+ );
+ SB_LUT4 #(
+ .LUT_INIT(16'b 0110_1001_1001_0110)
+ ) adder (
+ .I0(1'b0),
+ .I1(A),
+ .I2(B),
+ .I3(1'b0),
+ .O(O)
+ );
+endmodule
+EOT
+
+ice40_wrapcarry
+select -assert-count 1 t:$__ICE40_CARRY_WRAPPER