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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-08 10:53:44 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-08 10:53:44 -0700 |
| commit | 4c89a4e642c8618a0e18270d338e48599834d923 (patch) | |
| tree | 9cdc0a26a98880fd9f0f90e21db269d074901471 /tests/ice40 | |
| parent | 9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f (diff) | |
| parent | 84f978bdc20494167a6a2c5f654b96c4f565a5e0 (diff) | |
| download | yosys-4c89a4e642c8618a0e18270d338e48599834d923.tar.gz yosys-4c89a4e642c8618a0e18270d338e48599834d923.tar.bz2 yosys-4c89a4e642c8618a0e18270d338e48599834d923.zip | |
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync
async2sync to be called by equiv_opt only when -async2sync given
Diffstat (limited to 'tests/ice40')
| -rw-r--r-- | tests/ice40/latches.ys | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index f3562559e..708734e44 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,14 +1,11 @@ read_verilog latches.v -design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +# Can't run any sort of equivalence check because latches are blown to LUTs +#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load read +#design -load preopt synth_ice40 cd top select -assert-count 4 t:SB_LUT4 |