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authorNiels Moseley <n.a.moseley@moseleyinstruments.com>2019-03-27 15:15:53 +0100
committerNiels Moseley <n.a.moseley@moseleyinstruments.com>2019-03-27 15:15:53 +0100
commit487cb45b87ce1cbcc8c2b8127e37d85dd192dceb (patch)
treeb94e88d08574cf3ee10b8a7c0449b85fae75ca94 /tests/liberty/processdefs.lib
parent7682629b79fd59f5ed49fb35a3a2441a405bfd63 (diff)
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Liberty file parser now accepts superfluous ;
Diffstat (limited to 'tests/liberty/processdefs.lib')
-rw-r--r--tests/liberty/processdefs.lib48
1 files changed, 48 insertions, 0 deletions
diff --git a/tests/liberty/processdefs.lib b/tests/liberty/processdefs.lib
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+/********************************************/
+/* */
+/* Supergate cell library for Bench marking */
+/* */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley */
+/* */
+/* Process: none */
+/* */
+/* Date : 25-03-2019 */
+/* Version: 1.0 */
+/* */
+/********************************************/
+
+library(processdefs) {
+ technology (cmos);
+ revision : 1.0;
+
+ time_unit : "1ps";
+ pulling_resistance_unit : "1kohm";
+ voltage_unit : "1V";
+ current_unit : "1uA";
+
+ capacitive_load_unit(1,ff);
+
+ default_inout_pin_cap : 7.0;
+ default_input_pin_cap : 7.0;
+ default_output_pin_cap : 0.0;
+ default_fanout_load : 1.0;
+
+ default_wire_load_capacitance : 0.1;
+ default_wire_load_resistance : 1.0e-3;
+ default_wire_load_area : 0.0;
+
+ nom_process : 1.0;
+ nom_temperature : 25.0;
+ nom_voltage : 1.2;
+
+ delay_model : generic_cmos;
+
+ define_cell_area(bond_pads,pad_slots)
+ input_voltage(cmos) {
+ vil : 0.3 * VDD ;
+ vih : 0.7 * VDD ;
+ vimin : -0.5 ;
+ vimax : VDD + 0.5 ;
+ }
+}