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authorEddie Hung <eddie@fpgeh.com>2020-02-10 08:31:01 -0800
committerGitHub <noreply@github.com>2020-02-10 08:31:01 -0800
commitd4ff5b2d007c73cd95fa61bafdb65a47796014d9 (patch)
treefa5764c37cfcdb479acd7e6bce90e4cd7261ec88 /tests/memfile/memory.v
parent224dc033aad4081944e004e0e681d4606e9c9655 (diff)
parent9da5936c0555de28fc9d254242bd2a33b3399ad6 (diff)
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Merge pull request #1670 from rodrigomelo9/master
$readmem[hb] file inclusion is now relative to the Verilog file
Diffstat (limited to 'tests/memfile/memory.v')
-rw-r--r--tests/memfile/memory.v23
1 files changed, 23 insertions, 0 deletions
diff --git a/tests/memfile/memory.v b/tests/memfile/memory.v
new file mode 100644
index 000000000..57106eae8
--- /dev/null
+++ b/tests/memfile/memory.v
@@ -0,0 +1,23 @@
+// A memory initialized with an external file
+
+module memory (
+ input clk_i,
+ input we_i,
+ input [5:0] addr_i,
+ input [31:0] data_i,
+ output reg [31:0] data_o
+);
+
+parameter MEMFILE = "";
+
+reg [31:0] mem [0:63];
+
+initial $readmemb(MEMFILE,mem);
+
+always @(posedge clk_i) begin
+ if (we_i)
+ mem[addr_i] <= data_i;
+ data_o <= mem[addr_i];
+end
+
+endmodule