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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-06 16:30:56 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
| commit | 982a11c709b4b363f85ae52a127f8a98bda30a3f (patch) | |
| tree | de2dd78747314064b3a7731fc4791b0ec7bfb77d /tests/memlib/memlib_block_sdp.v | |
| parent | 2a2dc12eb69f2e904609e5b8275ec885e21ecd26 (diff) | |
| download | yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.tar.gz yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.tar.bz2 yosys-982a11c709b4b363f85ae52a127f8a98bda30a3f.zip | |
Add memory_libmap tests.
Diffstat (limited to 'tests/memlib/memlib_block_sdp.v')
| -rw-r--r-- | tests/memlib/memlib_block_sdp.v | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/tests/memlib/memlib_block_sdp.v b/tests/memlib/memlib_block_sdp.v new file mode 100644 index 000000000..d8dac68e3 --- /dev/null +++ b/tests/memlib/memlib_block_sdp.v @@ -0,0 +1,26 @@ +module RAM_BLOCK_SDP( + input PORT_R_CLK, + input [9:0] PORT_R_ADDR, + output reg [15:0] PORT_R_RD_DATA, + input PORT_W_CLK, + input PORT_W_WR_EN, + input [9:0] PORT_W_ADDR, + input [15:0] PORT_W_WR_DATA +); + +parameter INIT = 0; +parameter PORT_R_WIDTH = 1; +parameter PORT_W_WIDTH = 1; +parameter PORT_R_CLK_POL = 0; +parameter PORT_W_CLK_POL = 0; + +reg [2**10-1:0] mem = INIT; + +always @(negedge (PORT_R_CLK ^ PORT_R_CLK_POL)) + PORT_R_RD_DATA <= mem[PORT_R_ADDR+:PORT_R_WIDTH]; + +always @(negedge (PORT_W_CLK ^ PORT_W_CLK_POL)) + if (PORT_W_WR_EN) + mem[PORT_W_ADDR+:PORT_W_WIDTH] <= PORT_W_WR_DATA; + +endmodule |