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| author | KrystalDelusion <krystinedawn@yosyshq.com> | 2022-07-07 11:10:33 +1200 |
|---|---|---|
| committer | KrystalDelusion <krystinedawn@yosyshq.com> | 2023-02-21 05:23:15 +1300 |
| commit | 7f033d3c1f4604d303da237fbc7a38ee503416ad (patch) | |
| tree | ab936013736da16465f74fe771dd08f5fbf261d6 /tests/memlib/memlib_lut.v | |
| parent | af1b9c9e070dd5873871c73c5762fbefd345a8c9 (diff) | |
| download | yosys-7f033d3c1f4604d303da237fbc7a38ee503416ad.tar.gz yosys-7f033d3c1f4604d303da237fbc7a38ee503416ad.tar.bz2 yosys-7f033d3c1f4604d303da237fbc7a38ee503416ad.zip | |
More tests in memlib/generate.py
Covers most of the todo list, at least functionally. Some minor issues with not always using hardware features.
Diffstat (limited to 'tests/memlib/memlib_lut.v')
| -rw-r--r-- | tests/memlib/memlib_lut.v | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/tests/memlib/memlib_lut.v b/tests/memlib/memlib_lut.v index 1f20a110a..2685d2337 100644 --- a/tests/memlib/memlib_lut.v +++ b/tests/memlib/memlib_lut.v @@ -9,6 +9,7 @@ module RAM_LUT( ); parameter INIT = 0; +parameter OPTION_INIT = "UNDEFINED"; parameter PORT_RW_CLK_POL = 1; reg [3:0] mem [0:15]; @@ -16,7 +17,13 @@ reg [3:0] mem [0:15]; integer i; initial for (i = 0; i < 16; i += 1) - mem[i] = INIT[i*4+:4]; + case (OPTION_INIT) + "NONE": mem[i] = mem[i]; //? + "ZERO": mem[i] = 4'h0; + "ANY": mem[i] = INIT[i*4+:4]; + "NO_UNDEF": mem[i] = INIT[i*4+:4]; + "UNDEFINED": mem[i] = 4'hx; + endcase assign PORT_R_RD_DATA = mem[PORT_R_ADDR]; assign PORT_RW_RD_DATA = mem[PORT_RW_ADDR]; |